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From : Alexey Vladimirov 2:5100/73.1 Пон 03 Мар 97 18:23
To : Maxim Polyanskiy Чтв 06 Мар 97 04:43
Subj : 9386 (Было:93LC46P)
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Hello Maxim!
MP> А по 93с86 не кинешь?
По пеpвому pазу:
=== Cut ===
Цитата из "Non-volatile memory products data book", 1996/97. P. 4-69...4-78
93c86 - 16K (2048x8 or 1024x16) CMOS Serial Electrically Erasable PROM.
Pin configuration:
===== =====
CS -|1 U 8|- Vcc CS -|1===8|- Vcc
CLK -|2 7|- PE CLK -|2 7|- PE
DI -|3 6|- Org DI -|3 6|- ORG
DO -|4 5|- Vss DO -|4 5|- Vss
===== =====
DIP 93C86 SOIC 93C86
DC Characteristics:
min max conditions
High level input voltage, V 2.0 Vcc+1
Low level input voltage, V -0.3 0.8
High level output voltage, V 2.4 Ioh= -400 uA
Low level output voltage, V 0.4 Iol= 2.1 mA
Input leakage current, uA -10 10 Vin= 0.1V to Vcc
Output leakage current, uA -10 10 Vout= 0.1V to Vcc
Internal capacitance, pF 7 f= 1MHz
Operating current, read, mA 1 f= 3MHz, Vcc=5.5V
0.5 f= 1MHz, Vcc=3.0V
Operating current, write, mA 3 Vcc=5.5 mA
Standby current, uA 100 CLK=CS= 0V, Vcc= 5.5V
30 CLK=CS= 0V, Vcc= 3.0V
AC Characteristics:
min max conditions
Endurance 10M R/W cycles
Clock frequency, MHz Fclk 3 4.5<Vcc<6V
1 2.5<Vcc<4.5V
Clock high time, ns Tckh 100/250
Clock low time, ns Tckl 200/300
Chip select setup time, ns Tcss 50/100
Chip select hold time, ns Tcsh 0
Chip select low time, ns Tcsl 100
Data input setup time, ns Tdis 50/100
Data input hold time, ns Tdih 50/100
Data output delay time, ns Tpd 100/250 Cl=100 pF
Data output disable time (from CS=low), ns Tcz 100/500 Cl=100 pF
Status valid time, ns Tsv 200/300 Cl=100 pF
Program cycle time (Auto Erase & Write), ms Twc 5
Tec 15 ERAL
Twl 30 WRAL
Synchronous data timing:
Tckh Tckl
|______________| | | __________________
CLK______/| \\|_______________|/| \\___________
| |
|Tdis| Tdih | |
____ | __________ | _________________ _____________ ___________________
/\\ \\ / valid \\ /\\ /\\ /\\ /\\ /\\ /\\ \\ / valid \\ /\\ /\\ /\\ /\\ /\\ /\\ /\\
DI/_/ \\__________/ \\/_\\/_\\/_\\/_\\/_\\/_/ \\_____________/ \\/_\\/_\\/_\\/_\\/_\\/_\\/
| |
|Tcss | | Tcsl|
|__________________________________________________________| |____
CS___/ | | |\\___/
| | |
| Tpd | | Tpd | |Tcz|
__________________ | _____________________________ | _______________ |
\\ / valid \\ / valid \\|_HIGH_
DO________________/ \\_____________________________/ \\_______________/
Instruction set (ORG=1 - x16 organization)
instruct start opcode address number of data out CLK
bit OP1 OP2 data in cycles
READ 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 29
WRITE 1 0 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/^BSY) 29
ERASE 1 1 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/^BSY) 13
EWEN 1 0 0 1 1 X X X X X X X X High-Z 13
EWDS 1 0 0 0 0 X X X X X X X X High-Z 13
ERAL 1 0 0 1 0 X X X X X X X X (RDY/^BSY) 13
WRAL 1 0 0 0 1 X X X X X X X X D15-D0 (RDY/^BSY) 29
Instruction set (ORG=0 - x8 organization)
instruct start opcode address number of data out CLK
bit OP1 OP2 data in cycles
READ 1 1 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 22
WRITE 1 0 1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/^BSY) 22
ERASE 1 1 1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/^BSY) 14
EWEN 1 0 0 1 1 X X X X X X X X X High-Z 14
EWDS 1 0 0 0 0 X X X X X X X X X High-Z 14
ERAL 1 0 0 1 0 X X X X X X X X X (RDY/^BSY) 14
WRAL 1 0 0 0 1 X X X X X X X X X D7-D0 (RDY/^BSY) 22
=== Cut ===
Alexey Vladimirov avlad@mail.ormix.riga.lv [Microchip technical support]
--- GoldED/2 2.50+
* Origin: -=ORMIX=- http://www.ormix.riga.lv (2:5100/73.1)
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